In digital communications systems comprising transmission links, it is a primary goal to recover the transmitted data as faithfully as possible at the receiving end of a link. The bit error rate (BER) is an indication commonly used to characterize such systems.
Ideally, the BER is 0, but a number of impairments can affect the propagation of the signal resulting in signal degradation. Simple techniques of compensation, for example simple correction of the path frequency response such as boosting the high frequency components of the signal, are not adequate for dealing with high speed signals that may be severely degraded. Numerous other techniques have been proposed to overcome the effects of signal degradation. Some of these techniques are specific to the type of transmission medium, such as copper cable, radio propagation, links with multipath effects, or optical fiber, and all of them require a clock recovery circuit. The recovered clock is used to sample the received data.
A well known source of degradation in many communications systems is dispersion. The dispersion effect can be explained if we assume that the transmitted signal can be represented as the sum of its frequency components. In fiber optic systems, chromatic dispersion, polarization mode dispersion, and modal dispersion are the most common types of dispersion, causing the propagation characteristics to vary with frequency. The received signal is affected by the sum of these components, resulting in inter symbol interference (ISI) by spreading the energy of each optical pulse over neighboring bits. The dispersion can thus cause bit errors in the receiver by confusing 1s and 0s.
Dispersion is present in all optical systems, but its effects become worse over longer spans and at higher transmission speeds. Long-haul systems already incorporate optical compensation elements to correct for chromatic and polarization dispersion compensation.
A new alternative is electronic compensation. Electronic dispersion compensation (EDC) circuits have been proposed as a lower cost and lower power solution, see e.g. a copending U.S. patent application to Popescu entitled “High Speed Circuits for Electronic Dispersion Compensation” Ser. No. 10/638,386, filed Aug. 12, 2003, which is incorporated herein by reference.
A typical fiber optic communications system 10 with electronic dispersion compensation is illustrated in FIG. 1. Such a system includes a Transmitter 12, coupled to an electro-optic (E/O) converter 14, a fiber link 16, an opto-electrical (O/E) converter 18, an electronic dispersion compensation enabled (EDC) receiver 20, and an electronic dispersion compensation (EDC) controller 22.
A digital bit stream 24 from the transmitter 12 is sent to the E/O converter 14. The output of the E/O converter 14 is an optical signal 26 to be transmitted over the fiber link 16. The output of the fiber link 16 is an optical signal 28, coupled to the input of the O/E converter 18.
The output signal of the O/E converter 18 is an analog signal 30. The EDC Receiver 20 receives the analog signal 30, and outputs a digital data signal 32 and a recovered clock 34. The digital data signal 32 may be coupled to an input of the EDC controller 22 (dotted line), the output of which is a set of control signals 36, coupled to a control input 38 of the EDC Receiver 20.
As described above, degradation caused by dispersion distorts the signal transmitted by the fiber link 16. As a result, the analog signal 30 at the output of the O/E Converter 18 is not an exact replica of the digital bit stream 24 that was sent by the transmitter 12.
The purpose of the EDC Receiver 20 is to process the analog signal 30 into the digital data signal 32, and be as close a representation of the original digital bit stream 24 as possible. The method used by the EDC Receiver 20 is generally based on the idea of reversing the impairment (dispersion) caused by the fiber link.
A direct approach to improving the performance of digital transmission systems is to consider the geometry of the signal eye and apply adaptive compensation circuitry to correct the degradation prior to sampling the signal, such adaptive compensation circuitry requiring an accurate sampling edge position of a high speed signal.
For example, in U.S. Patent Application 20040037572 to Matsuyama published Feb. 26, 2004, the signal path, prior to discrimination into 1s and 0s, is processed by band pass filters and equalization filters where the equalization filter coefficients are computed to compensate both frequency dependent loss and group delay distortions. The computation is done in the frequency domain using Fast Fourier Transform (FFT) techniques, based on time shifted samples of the received waveform. While this method may theoretically be used to realize high-accuracy compensation for waveform degradation of a received signal stemming from chromatic dispersion, polarization mode dispersion or the like without employing a dispersion compensation fiber or a polarization maintaining fiber, it is an expensive method, requiring a large amount of very high speed circuitry.
A different approach, in which additional compensation is based on direct observation of the received eye is disclosed in U.S. Patent Application 20030011847 to Dai, Fa et al. published Jun. 5, 2002. This technique is based on a complex feedback system which includes estimating error rates by sampling the eye with variable delays in time X-detect) and variable voltage thresholds (Y-detect), periodically evaluating the results in a digital signal processor (DSP), and re-adjusting the variable sampling parameters, as well as adjusting feed forward equalizer (FFE) and decision feedback equalizer (DFE) parameters.
Unfortunately, the method proposed by Dai et al. (US2003/0011847) is not practical to implement for high speed applications. This solution will require significant power dissipation, and its implementation is distributed amongst several integrated circuits. In particular, it requires two high speed counters, two programmable high speed delay circuits, a VCO with quadrature outputs, and an external DSP, the function of which is insufficiently explained. The high speed counters and the high speed programmable delay circuits, operating at 10 GHz or higher clock frequency, will dissipate a significant amount of power, and as a result will make such a circuit impractical to implement. Generating the high frequency quadrature clock and the need to distribute in-phase and quadrature clocks to many blocks, while maintaining the phase relationship between the clocks, makes this prior art solution impractical for operation at 10 GHz or higher frequency clocks. It is difficult to generate precise variable delays at 10 GHz, consequently the eye-open X-Detect may generate inaccurate results. Nor is it possible to calibrate and confirm its efficacy as the absolute variable delays cannot be calibrated or measured.
While certain ways of performing sampling edge positioning have been described in the cited prior art references, what is still required is a much simpler, yet reliable method and circuitry for locating the sampling edge position, which would be especially applicable to the recovery of high speed signals, such as those of 10 and 40 Gbps fiber optic links, in the presence of signal eye degradation.